The invention relates to a charge transfer device comprising a row of clock electrodes defined on a surface of a semiconductor body for supplying clock voltages for transporting information-representing charge packets through a charge transfer channel in the body to a reading stage at which transported charge packets can be detected, the reading stage being so constructed such that, during at least substantially the whole clock period, output signals can be derived therefrom which are constant and representative for the information to be read.
Charge transfer devices having the features described in the first paragraph are known inter alia from "Handbook on Semiconductors", ed. T. S. Moss, Volume 4, ed. C. Hilsum, chapter 3B, pp. 397-401, FIG. 39, p.398. This publication shows an output which is known as a "correlated double sampling output". In this output, a charge packet is transported to an output diode which is first biased to a reference voltage or reset voltage. The charge packet induces a voltage variation in the diode, which is supplied to a first amplifier, especially a source follower, whose input is connected to the diode. The output of the source follower is coupled in turn to the input of the output amplifier through a switch. When the switch is closed, the signal supplied by the source follower, which is a measure of the charge packet to be read, is supplied to the output amplifier, after which the switch can be opened again. After the switch has been opened again, the diode can be brought to the reference voltage again for a next charge packet to be read. Meanwhile, the output amplifier continues to supply an output signal representative of the first charge packet. The second charge packet can be transferred to the diode and can be detected by the source follower. The switch can then be closed again, while an output signal representative of the second charge packet can be derived from the output of the output amplifier.
Rectangular signals having a width (duration) of a clock period can be derived from the output of the output amplifier. The output voltage consequently does not return between two successive signals to a reference level, as is the case, for example, with the output signal of the source follower. As is indicated in the said publication with reference to FIG. 40, the alternation between signal and reference level gives rise to spectra of higher orders of the signal at the output, which have to be eliminated entirely or in part for many applications by additional steps. In order to eliminate these signals of higher orders, expensive filters are often required. When to the contrary a rectangular output signal is supplied during the whole clock period, these spectra of higher orders are automatically suppressed to a large extent.
A disadvantage of the known device described here is the limitation in the clock frequency at which the device can be operated, which means a limitation for the bandwidth of the signals to be processed. It has been found in practice that the maximum clock frequency lies between 15 and 25 MHz. For many applications, especially in the field of video signal processing, considerably higher frequencies are required. An important cause of this frequency limitation resides in the fact that the output diode must be brought back to the reference level through a switch each time between two successive signal detections. Moreover, the switch between the source follower and the output amplifier, which switch is generally constituted by a MOS transistor, brings about a certain delay, which in case the output diode does not constitute the main limiting factor for the clock frequency, will impose a serious limitation on the maximum clock frequency.
An additional disadvantage of this switch resides in cross-talk of the clock voltage with which the switch is operated to the output signal.
An additional disadvantage of this switch resides in cross-talk of the clock voltage with which the switch is operated to the output signal.